1. Field of the Invention
The present invention relates to a control circuit for driving a current-driven display unit using organic electroluminescent devices (hereinafter called “EL devices”), light-emitting diodes (hereinafter called “LEDs”), etc. which respectively emit light according to the supply of currents.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional control circuit.
The conventional driver principally comprises a driver circuit unit 10, a control voltage generating circuit 20 and EL devices D1 through D6. The driver circuit unit 10 comprises a plurality of drive current output circuits Dr1 through Dr6. The drive current output circuits Dr1 through Dr6 output a drive current to the corresponding EL devices D1 through D6. Specially, the drive current output circuit Dr1 outputs the drive current to the EL device D1. The control voltage generating circuit outputs a control voltage Vc1 to the drive current output circuit Dr1 through Dr6 for controlling the current outputted from the drive current output circuits Dr1 through Dr6.
The control voltage generating circuit 20 is connected between a power node Vdd that is applied a power supply voltage and a ground node Vss that is applied a ground potential. Each of an anode of the EL devices D1 through D6 are connected to each of the drive current output circuits Dr1 through Dr6, and all of a cathode of the EL devices D1 through D6 are connected to the ground node.
Each of the drive current output circuit Dr1 through Dr6 has a same structure and each of which includes two p-channel metal-semiconductor-oxide (hereinafter called “PMOS) transistors. For example, the drive current output circuit Dr1 includes a PMOS transistor Q1 and a PMOS transistor Q2. The PMOS transistor Q1 has a source connected to the power node Vdd, a gate connected to the control voltage generating circuit 20 and a drain. The PMOS transistor Q2 has a source connected to the drain of the PMOS transistor Q1, a drain connected to the anode of the EL device D1, and a gate that is applied a switching signal S1. Also, the PMOS transistors Q3, Q5, Q7, Q9 and Q11 of other drive current output circuit Dr2 through Dr6 are connected between the power supply voltage Vdd and the control voltage generating circuit 20, respectively.
When the switching signal S1 is applied to the gate of the PMOS transistor Q2 of the driver circuit Dr1, the PMOS transistor Q2 is turned on. Then the PMOS transistor Q2 outputs a current Id1 to the EL device D1 for driving the EL device D1. Also, each gate of PMOS transistors Q4, Q6, Q8, Q10 and Q12 is applied switching signals S2, S3, S4, S5 and S6, respectively. The drive current output circuits Dr2 through Dr6 respectively output the drive currents Id2 through Id6 to the EL devices D2 through D6, in response to input the switching signals S2 through S6. The drive currents Id2 through Id6 drive the EL devices D2 through D6.
The control voltage generating circuit 20 includes a PMOS transistor Q21, a PMOS transistor Q22, a resistor R1 and an operational amplifier OP1. The operational amplifier OP1 has an inversion terminal that is applied the reference voltage Vref, a non-inversion terminal and an output terminal. The PMOS transistor Q21 has a source connected to the power supply voltage Vdd, a drain and a gate connected to the output terminal of the operational amplifier OP1. The PMOS Q22 has a source connected to the drain of the PMOS transistor Q21, a drain connected to the ground potential Vss via the resistor R1 and a gate connected to the non-inversion terminal of the operational amplifier OP1.
The gate of the PMOS transistor Q1 of the drive circuit Dr1 is connected to the output terminal of the operational amplifier OP1. Since the gate of the PMOS transistor Q1 is connected to the gate of the PMOS transistor Q21, these two transistors Q1 and Q21 constitute a current mirror circuit. Thus, a current flows through the PMOS transistor Q1 is determined based on a ratio between a dimension (corresponding to a ratio W/L between the width of the gate of the PMOS transistor Q21 and the length of its gate) of the PMOS transistor Q21 and a dimension (corresponding to a ratio W/L between the width of the gate of the PMOS transistor Q1 and the length of its gate) of the PMOS transistor Q1. Also, each of the PMOS transistors Q2 through Q6 is constitute a current mirror circuit with the PMOS transistor Q21.
The operational amplifier OP1 outputs a control voltage Vc1. The control voltage Vc1 is applied to the gate of the PMOS transistor Q21 and the driver circuits Dr1 through Dr6. The operational amplifier OP1 controls the control voltage Vc1, such that the reference voltage Vref and the voltage applied on the drain of the PMOS transistor Q22 become equal. Therefore, the operational amplifier OP1 outputs the reference voltage constantly. Since the operational amplifier OP1 keeps the output voltage constantly, the PMOS transistor Q21 keeps the current Iref constantly. The PMOS transistor Q21 and the PMOS transistors Q1, Q3, Q5, Q7, Q9 and Q11 constitute a current mirror circuit. That is, when the dimensions of these transistors Q1, Q3, Q5, Q7, Q9, Q11 and Q21 are equal, the currents Id1 through Id6 and the Iref are equal.
FIG. 2 shows a layout of the control voltage generating circuit 20 and the driver circuit unit 10 on the semiconductor substrate 100.
On the semiconductor substrate 100, the control voltage generating circuit 20 is located near the drive circuit unit 10. The power supply voltage Vdd is supplied to the control voltage generating circuit 20 and the drive circuit unit 10. The control voltage generating circuit 20 supplies the control voltage Vc1 to the drive circuit unit 10. The EL devices D1 through D6 are provided outside of the semiconductor substrate 100. The drive current output circuits Dr1 through Dr6 are located along the direction A in series.
In design of the driver, the currents Id1 through Id6 are approximately equal each other. However, when few hundred of the drive current output circuits are formed on the semiconductor substrate 100 in series, the length of the driver circuit unit 10 in the direction A as shown in FIG. 2 is expanded. Each of the transistors Q1 through Q12 in the respective drive current output circuits Dr1 through Dr6 are designed so as to have a same characteristic. However, each of the transistors that are manufactured on the semiconductor substrate has a various characteristics. As a result, it may be different from the characteristic of the transistor in the drive current output circuit located near the control voltage generating circuit to a characteristic of the transistor in the drive current output circuit located far from the control voltage generating circuit. That is, the current outputted from the drive current output circuit that is located far from the control voltage generating circuit 20 may be different from the reference current Iref.
FIG. 3(a) shows the control voltage Vc that is applied to the each drive current output circuit Dr1 through Dr6. FIG. 3(b) shows various current values Id1 through Id6 which change based on respective distances from the control voltage generating circuit 20 to the drive current output circuits Dr1 through Dr6.
FIG. 3(b) shows that the current Id1 outputted from the drive current output circuit Dr1 that located nearest to the control voltage generating circuit 20 is larger than the current Id6 outputted from the drive current output circuit Dr6 that located farthest from the control voltage generating circuit 20. That is, the current value outputted from the drive current output circuit decreases as the distance increases.
Accordingly, an object of the present invention is providing a control circuit to reduce the variation of the current values from each drive current output circuit.